Pawan Kumar Sanjaya

Pawan Kumar Sanjaya

PhD Student

University Of Toronto

embARC Research Group

Biography

Pawan is an aspiring researcher in Computer Architecture primarily focussing on heterogeneous systems and domain specific architectures. He is currently pursuing his PhD in Computer Science at University of Toronto.

Interests
  • Heterogeneous Architectures
  • Hardware Security
  • Domain Specific Hardware Design
Education

  • PhD in Computer Science, 2023-

    University of Toronto

  • Bachelor of Technology(hons) + Master of Technology in Computer Engineering, 2016-2021

    IIITDM Kancheepuram

Projects

*
All RISC-V arch-test
RISCOF: RISC-V Compatibility Testing Framework
A framework to filter, configure, run and validate architectural tests on a given RISC-V implementation based on the configuration.
Code Docs
RISCV-CONFIG: RISC-V Configuration Validator
A python based validator to validate the configuration of a RISC-V implementation using a yaml based format. The specification format is scalable to handle all possible architectural options as allowed by the RISC-V specification, including WARL functions of CSRs.
Code Docs
RISCV-CTG: RISC-V Coverage Driven Test Generator
Due to the highly permissive nature of the RISC-V ISA, manually writing high quality architectural compatibility tests is infeasible. This tool models tests as a set of constraint satisfcation problems(CSP) in finite domain using the architectural fields as variables and coverage goals as constraints. The solutions to these problems are found using CSP solvers and converted into RISC-V assembly programs using handwritten templates.
Code Docs
RISCV-ISAC: RISC-V ISA Coverage Generator
Defines an open source coverage specification format using only the fields in the ISA. Thereby, providing a free, independent and scalable coverage measurement tool for Architectural Compatibility Testing. It also analyses the instruction trace to provide data propagation reports which are critical for memory signature based tests. The data propagation reports ensure that bugs in the implementation manifest as mismatched signature when compared with the golden model.
Code Docs

Publications

S Pawan Kumar, Shrreya Singh, Neel Gala, Allen Baum. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V. Sixth Workshop on Computer Architecture Research with RISC-V, Co-located with ISCA, 2022.
PDF Cite Slides riscv-isac riscv-isac

Recent & Upcoming Talks

Using riscof for RISC-V Architectural Testing
A tutorial on getting started with riscof for performing RISC-V Architectural Testing on implementations.
Dec 15, 2022 12:00 AM
Project Slides Video

Experience

 
 
 
 
 
RTL Design Engineer
InCore Semiconductors Pvt. Ltd.
Jun 2021 – Aug 2033
  • Design and implement micro-architectural improvements for a 6stage in-order RISC-V Cores.
  • Design Multi-core RISC-V processor with hierarchial and coherent Caches.
  • Conceptualised and directed implementation of various features for key tools in the RISC‐V Architectural Testing ecosystem for testing various extensions in the specification.
 
 
 
 
 
RTL Design Intern
InCore Semiconductors Pvt. Ltd.
May 2021 – Dec 2020
  • Explore automatic generation of coherent cache subsystem from SSP.
 
 
 
 
 
Research Intern
SHAKTI initiative, RISE Labs, IIT Madras
May 2020 – Oct 2020 Chennai
  • Designed and implemented a secure boot solution for Shakti RISC‐V cores. The solution consisted of a signing tool, framework and run‐time libraries to be integrated with the firmware.
  • Designed extensions to support higher level API calls and provide better security guarantees.
  • Proposed a scheme to support trusted execution environments using a co‐processor by analysing various solutions such as Intel SGX, Sanctum and Keystone.
 
 
 
 
 
Summer Research Intern
SHAKTI initiative, RISE Labs, IIT Madras
May 2019 – Jul 2019 Chennai
  • Evaluated various methods to generate bluespec code for SOCs based on a given configuration. Implemented a tool which could automatically generate SOCs with optimal address mappings for heterogeneous and hierarchical busses.
  • Identified key csr configuration options in the RISC‐V ISA and designed a scheme to describe the custom behaviours. Implemented an open‐source tool(riscv-config) in python to validate descriptions and verify legality of behaviours.
  • Evaluated various strategies for RISC‐V architectural compliance testing and implemented a dynamic, scalable and easy‐to‐use open‐source framework(riscof) based on the best strategy.
 
 
 
 
 
Research Intern
SHAKTI initiative, RISE Labs, IIT Madras
May 2018 – Jul 2018 Chennai
  • Designed and developed a pipelined and multi‐cycle SHA 256 accelerator in Bluespec System Verilog.
  • Optimised the design for area, delay and power on the Xilinx Artix‐7 FPGA.
  • Verified the correctness using NIST test vectors

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