RISCV-CTG: RISC-V Coverage Driven Test Generator

Due to the highly permissive nature of the RISC-V ISA, manually writing high quality architectural compatibility tests is infeasible. This tool models tests as a set of constraint satisfcation problems using the following:

  • architectural fields defined by the ISA (as variables)

  • coverage defined by RISCV-ISAC (as constraints)

The solutions to these problems are found using CSP solvers and converted into RISC-V assembly programs using handwritten templates.

Pawan Kumar Sanjaya
Pawan Kumar Sanjaya
PhD Student

My research interests broadly lie in the domains of Computer Architecture, Hardware Security and Systems.